PC Support Departments are a relatively new phenomemon, and the whole area of expertise has itself only developed in the last few years in response to corporate acceptance of PCs. This means that there is little formal training in the area, and no career path that leads to a PC support position (or from it, for that matter).

The area of training is particularly important, since many support people come from a software background and have no experience with hardware. With this in mind, we intend to provide more introductory material on hardware than on software - starting here.

In this series of articles, we shall cover topics like basic principles of electricity, identification of components and boards, maintenance by board swapping, keyboard maintenance, cable making, memory chip replacement and all the other hardware 'tricks of the trade' we can discover.

A PC Support Toolkit

Before you can tackle hardware support tasks, you will need tools. As Churchill said, "Give us the tools, and we will finish the job". Here's what you'll need:

A selection of screwdrivers. Avoid metal-handled jeweller's screwdrivers: if applied to live wiring, the handle becomes live, and then you do, too. While small jeweller's scredrivers are useful for fine work, you are unlikely to get involved with this. Instead, choose screwdrivers with an amber plastic handle. Small screwdrivers which may be used for making adjustments should have a plastic sleeve down the length of the blade.

While some of the screws on your PC's may be domed or cheese-head screws for a flat blade, others are likely to require a 'cross- point' or Phillips screwdriver. Increasingly these are actually Pozidriv screws.

If you are working on Apple Macintoshes or Compaq equipment you will need Torx T-10 and T-15 screwdrivers.

Nut drivers may also be useful occasionally, but they are not a high priority.

For making adjustments to high voltage circuitry, such as monitors, a plastic trimming tool is essential.

Pliers - needle-nosed pliers are extremely useful for holding nuts, wires when cablemaking and countless other purposes. Flat pliers are less useful. Wire cutters or snips are essential also; do not rely on a wire-cutting edge on conventional pliers.

A wire stripper is useful for those who have not developed the delicate touch necessary to strip back insulation on wires with wire cutters.

A soldering iron is essential for cable-making, A temperature- controlled iron with stand is best, but a simple 25W (25 watt) iron fits into a toolbox or bag more easily and is adequate for simple jobs.

A chip puller is used to extract integrated circuits from their sockets without unduly stressing them - particularly important in the case of ceramic-cased chips, as they are fairly brittle. While chips can be levered up with a screwdriver blade, this must be done cautiously.

Your toolkit should also include some software: Advanced Diagnostics for the IBM PC family and similar diagnostics from other suppliers, together with blanking and loop-back connectors for diagnostic purposes, as well as PC Tools, Norton Utilities, MACE Utilities and similar file recovery and disk unformatting utilities.

How to disassemble a PC

Disassembling a PC is quite simple, really.

Step 1. Switch off the power at the wall socket and unplug the machine. Leave the plug where you can see it. Most machines have a connector at the back where the power cable is plugged in; this is called an IEC (International Electrotechnical Commission) connector, and you will generally want to unplug the cable at this end, too.

Repeat this step for any attached devices, such as the monitor, which are going to be moved.

Step 2. Unplug the monitor, printer and other data cables. You may find that these devices are attached through what are called D-type connectors, which often have attaching screws at the top and bottom, which must be undone before the cables can be removed. A flat-bladed screwdriver will be required for this job.

Step 3. Remove the monitor from its position on top of the machine and place it to one side. The floor is a good place: the monitor can't fall off it.

Step 4. Slide the machine forward if necessary, so that you have access to the rear panel. You should find four large screws at the left and right top and bottom of the panel, with a fifth at the top centre. Undo these screws, and place the screws to one side. The small black plastic canisters used for 35mm film are very useful for this purpose.

Step 5. From the front of the machine, slide the cover towards you until it is almost off the machine. At this point, it will bump to a stop and you should raise the front of the cover so that the bottom of the cover clears the front of the chassis and then lift the cover away. The internals of the PC are now visible.

What you will see obviously depends upon the particular machine, but the general outline is usually the same. At the right rear, facing from the front of the machine, is a large metallic box, possible with louvred vents in it. This is the power supply and fan assembly. There is not much that is user-serviceable in there, so you will treat it as a complete subassembly and remove or install it as a unit.

In front of the power supply, at the right front side of the machine, are the disk drive bays. In XT-class machines, there are usually two bays, which will either contain two floppy disk drives or one floppy drive and a hard disk drive. The floppy disk drive has an open mechanism and you can see where the disk slides in, as well as the clutch which grips and spins the disk, and the head assembly.

The hard disk, on the other hand, is a sealed unit, although you may not be able to see that because of the drive controller circuitry, depending on how the drive is mounted.

For both types of drives, the most common form of mounting is by screw holes on the sides of the drives - usually two screws on each side. These may be flat or Phillips, depending on who assembled the PC.

Occupying the centre and left side of the machine is the system board (what IBM terms the 'planar board'). This contains the processor and assorted support chips, plus the main system memory. Usually, on XT's, for example, the processor is in the top centre/right of the circuit board. You can identify it by its part number - 8088 or 8086.

Usually, there will be an empty socket nearby which is reserved for the 8087 floating point processor.

To the left of the processor area, you will see a row of large connectors, some or all of them occupied by circuit boards. This is the expansion bus. In front of this, somewhere, you should find a regular array of chips which is the system board memory. These chips will have numbers like 4164 or 41256.

The system board carries other circuitry, such as the interrupt controller, DMA controller, keyboard interface, and in the case of an AT, a real time clock circuit. These are, for the most part, individual components which are difficult to locate on the system board; we shall deal with the circuitry in depth in the next article in this series.

The expansion cards which stand vertically at the rear left will include a graphics display card, probably one or more memory boards or multifunction boards, some serial ports and a parallel port. Later in this series we will learn how to identify the boards.

Disassembling a PS/2 Model 50

If you don't have a PC, but have access to PS/2 machines, take a look at the Model 50.

Step 1. Switch off the power and unplug the machine.

Step 2. Remove the monitor from the top of the machine. Now undo the two thumbscrews at the top of the rear panel, and you can slide the cover forward about half an inch and then lift it straight off.

Step 3. With the cover removed, you can see the 3 1/2" floppy drive at the front of the machine, and the hard disk towards the rear centre. Running down the right side of the machine, behind the power switch, is the power supply, while the fan is mounted on a post at the rear and the loudspeaker near the front.

Step 4. Both the disk drives are mounted onto the supporting chassis by spring clips moulded into the chassis. Depress them and slide the drives out. You can now lift the 'pop' fasteners which retain the chassis and lift it out to reveal the system board.

Step 5. Although the PS/2 Model 50 system board (or 'planar board', as it is termed by IBM) is much denser than that of the 'classic' PC/XT, it contains much the same functionality, and Figure 1 shows the locations of the major components on the board.

PS/2 Model 50 Planar Board

If you look closely at the construction of a personal computer, you will see the various components on the system board and the various plugged-in peripheral boards. To the uninitiated, it all looks like a tangled web of wires and fragile circuit boards - but it's not.

The main system board is generally arranged to lie flat in the chassis tray of the PC. The system board usually carries the processor, base random access memory, ROM BIOS and support circuitry such as the interrupt controller, keyboard interface and other bits and pieces. Let's start with the processor.

Processor Circuitry and Operation

The processor used in most personal computers - statistically speaking - is the Intel 8088. Fortunately, later processors such as the 80286 and 80386 have much in common with the 8088, so that we can run the same software on AT's and PS/2's, and this will simplify our discussion. The 8088 processor in turn is based on the earlier 8086.

The 8086 and 8088 processors are split into two, independently operating, units called the execution unit and the bus interface unit. The execution unit contains the general-purpose registers of the processor, together with its control logic, and in general terms, equates to the arithmetic and logic unit of more traditional computer designs. The bus interface unit generates addresses using a set of four special-purpose registers, and pre-fetches instructions and data from memory, feeding them to the execution unit through a short 'pipeline'. Because of this queue of instructions waiting to be executed, the execution unit is generally able to keep running even when the bus interface unit has stopped temporarily to allow other devices to access memory - the BIU can refill the queue later.

The execution unit contains a set of general-purpose 16-bit registers as shown. Notice that although many instructions can operate on any of the data registers, certain registers fulfil specific functions on specific instructions. For example, the CX register is used to count iterations through a loop, and instructions such as JCXZ (jump when CX = 0) depend upon CX being the loop counter. Likewise, SI and DI are used as pointers to strings, when copying, searching or otherwise manipulating strings.

It takes a little time for the programmer to become familiar with the functions of the different registers; however, high-level language compilers have no such difficulty, and are able to generate extremely efficient code for this architecture. Incidentally, the 80286 has the same register set, and while the 80386 has 32-bit registers, the bulk of existing software - especially under DOS - simply uses the lower sixteen bits of each register in a manner identical to the 8086. The extra registers on the 80386 are simply ignored.

The complete instruction set of the 8086 processor is shown in the accompanying table. The intention is not to enable you to become an asssembly language programmer, but just to serve as a reference for what follows and also to enable you to make some sense of the occasional assembler listings which appear in these notes.

Each of the instructions operates in several different addressing modes. This means the the operand of the instruction could be an immediate (constant) value, or the contents of a register or memory location. In the latter case, the address could be specified as a particular, absolute address, or as a location pointed to by a register, or by a pair of registers (as happens when working with arrays - one register points to the start of the array and the other provides an offset or index into the array. This is the 8086/88 programmer's second area of difficulty - learning which addressing modes work with which instructions - again, the compiler finds it easy.

However, there is one very important way in which all instructions share a common method of generating addresses, and it relates to the way in which the 8086 - a sixteen-bit CPU - is able to generate 20-bit addresses.

This involves the cooperation of the execution unit - which contains the general-purpose registers and the arithmetic and logic unit (ALU) - and the bus interface unit, which contains some special-purpose segment registers and special logic which pre-fetches instructions and data and passes them through a short pipeline to the execution unit.

Take the example of a program which is about to start execution, at location 40100H in memory (this is just above 256K - and not unlikely in modern systems). In this case, the code segment register will contain the value 4000H (four hex digits = 16 bits), while the Instruction Pointer - which points to each successive instruction in a program - will contain the value 0100: again, 16 bits.

This is where the special logic of the BIU swings into action. First, it takes the value in the CS register and multiplies it by 16. In hexadecimal, this means that it tacks a zero on the end, but since the processor operates on binary numbers it left-shifts the value four bits, sticking four zeros on the end. Now it adds on the value in the IP register, to give the desired result:

CS: 4000
CS x 16: 40000
+ IP: 00100
Result: 40100

Take a look at the following figure, which shows this diagramatically. Although this process obviously occurs arithmetically inside the processor, it is helpful to think of it graphically. You can see that the CS register points to an address in memory which is the start of the Code Segment, while the IP register specifies an offset from that point, into the Code Segment.

Address construction in 80x86 family processors.

Because the address is made up of the contents of two separate registers in the two different parts of the CPU, it is usually written that way, and not as a five-digit hex number as shown above. So, in the example above, the address would actually be 4000:0100, where 4000 is the segment address and 0100 is the offset. Addresses on the 8086 family of processors are almost always specified as segment:offset pairs.

In this example, I have shown the fetching of the first instruction of a program from its code segment. However, all data fetches and other references to memory are handled in exactly the same way. In fact, the various registers of the EU are usually paired, by default, with a matching segment register in the BIU. For example, the SI register is usually paired with the DS (Data Segment) register, and used to access dat in the data segment, while DI is paired with ES, the Extra Segment Register. BP and SS are both matched with the SS (Stack Segment) register. Another little trick the 8086 programmer has to master is remembering which registers are paired by default. However, it is possible for the programmer to override the default behaviour of the processor by specifying a segment override prefix, allowing him, for example, to fetch data from the code segment.

Because a segment register is always multiplied by 16 (left shifted four bits) by the BIU before an offset is added, segments must always begin on a 16-byte boundary - a minor restriction. And because the offset is held in a 16-bit register, the maximum offset value is 65535, leading to a maximum segment size of 64 Kbytes. Now you know why programmers often rail against the 8086 architecture - it's because of the necessity to split programs up into multiple code and data segments, and because of the difficulty in dealing with data objects (like spreadsheets or other large arrays) which are larger than 64K.

The difference between the 8086, which was the first 16-bit processor designed by Intel, and the 8088 which is used in IBM PCs, XTs and compatibles, is not a major one. Both processors have exactly the same Execution Unit, but the Bus Interface Unit is slightly different. The reason for this is that Intel also have an earlier 8-bit processor, the 8085, and the interface logic to the outside world on this processor is, naturally enough, similar in design. This in turn led to a similar pin-out on the 8086, the major difference being that the 8086 reads and writes 16 bits of data at a time, and sends out 20 address bits rather than 16.

Incidentally, all these processors use a common bus for address and data signals, sending out an address first, which must be latched (remembered or held) by outside circuitry, followed by a read or write of data on the same lines.

Sine the pinouts of the 8086 and 8085 were broadly similar, it was decided to produce a version of the 8086 which had a much closer - near-identical - pinout to the 8085. Although a 16-bit processor internally, this machine would only be able to read or write 8 bits of data at a time, since it would only have an 8-bit data bus, like the 8085. Hence the 8088 has the same Execution Unit as the 8086, but its Bus Interface Unit only reads or writes 8 bits at a time. This means that fetching a 16-bit instruction or data word will require twice as long on the 8088 as on the 8086, although in practice this does not slow the 8088 down to quite that extent because often the BIU is able to prefetch instructions and data faster than the EU can digest them.

On the benefit side, the 8088 is able to work easily with the family of support chips which Intel had designed for the earlier 8085, including RAM, ROM and parallel I/O chips. This, together with the fact that only eight data bits had to be latched and buffered, made for smaller and cheaper designs. In fact, somewhere in my collection of computer curia and trivia, I have an 8088-based single-board computer designed by Intel in 1979, which can support two users simultaneously running Tiny BASIC, yet is only the size of a playing card!

It was this low cost and compatibility with existing support chips which attracted IBM to the 8088 for their PC design in 1980. It is possible, just possible, that IBM had earlier designed an 8-bit CP/M-based PC, and only decided quite late in the design cycle to switch to the 16-bit 8088.

So much for the internal logic of the processor. Let's turn to its physical realisation.

Semiconductors - Operation and Handling

Like many of the semiconductor components in a PC, the processor is an example of a MOS VLSI circuit. MOS stands for Metal Oxide Semiconductor, and refers to the way in which the circuit is created (the correct jargon is fabricated) and operates. Unlike the conventional transistors and integrated circuits found inside radios, TVs and othe consumer electronics, the MOS integrated circuits used in computers are based upon field effect transistors. These transistors have the benefit of offering a very high resistance to an electric current when switched off, and a fairly low resistance when switched on, and a very limited range of behaviour in between. Thus, with two of these transistors arranged in series - one switched off, one switched on - very little current will flow.

This gives rise to the first benefit of such circuitry - low power consumption. In fact, there are several types of MOS circuitry. The first type, PMOS (p-channel MOS), was used in early processors such as the original Intel 8008. Its successor, NMOS (n-channel MOS) offers lower power consumption and greater circuitry density. Many processors, including the 808x family, are based upon this technology, or variants of it (Intel actually term their process HMOS, for high-performance MOS).

There is another form, called CMOS, for complementary metal oxide semiconductor, which actually combines a p-channel transistor and an n-channel transistor in each logic element. This is the variant that uses two transistors in series, always with one off and one on, so that most of the time, no current flows. In fact, current will only flow while the circuit is switching states. This gives rise to extremely low power consumption. Some companies, such as Harris, have been able to design CMOS versions of the 8086 and other NMOS processors. Such CMOS variants are usually identified by a C in their part number, such as 80C86.

This is particularly important in relation to the second benefit of MOS technology. Because the individual transistors in a MOS integrated circuit are so small (and getting smaller), semiconductor companies can fit more and more circuitry into a chip. Typical microprocessors today have in excess of 200,000 transistors on the chip. Hence the terms LSI (large scale integration) and VLSI (very large scale integration). Presumably ULSI lies just around the corner in the form of the 80486!

A little high-school physics reveals a problem, in the form of the law of conservation of energy. Although integrated circuits consume power, that energy does not just disappear. It re-emerges in the form of heat. This is why designers have shifted from NMOS to CMOS for the latest generation of processors such as the 80386 and the 68030. An 80386 processor made from NMOS logic would simply melt!

Bear in mind also that CMOS gates only consume power (read heat up) when they are switching state. It follows that the more they switch, the more power they consume and the hotter they get, and hence, the faster the processor the higher the power consumption and the higher the temperature. It is not unusual to see processors in high performance machines, such as supermicros and some minis, with heat sinks stuck on top - arrangements of fins which help to dissipate the heat.

Chip types & boards which use them
1488 RS-232C line driver Serial interface cards
2114 1k x 4 static RAM
2708 EPROM
2716 EPROM
2732 EPROM
6845 CRT controller chip MDA, CGA, EGA type boards
765A Floppy Disk controller chip
8048 Single-chip microcontroller Keyboards
8051 Single-chip microcontroller Keyboards
8086 Processor
8087 Floating point coprocessor
8088 16-bit processor with 8-bit bus interface
80186 16-bit processor
80188 16-bit processor with 8-bit bus interface
80286 16-bit processor
80287 Floating point coprocessor
80386 32-bit processor
80387 Floating point coprocessor
80386SX 32-bit processor with 16-bit bus interface
8237A DMA controller
8254 Programmable interval timer
8259A Interrupt controller
8284A Clock generator circuit
8288 Bus controller
4116 16k x 1 dynamic RAM Memory boards (old!)
4164 64k x 1 dynamic RAM Memory boards
41256 256K x 1 dynamic RAM Memory boards
Anything beginning 74, 74LS, 74A, etc is a TTL logic chip
PVGA1 Paradise Video Graphics Array Chip VGA boards
14418 Real-time clock circuit System Board
8259A Interrupt controller circuit System Board
8253 Counter/timer circuit System Board
8254 Counter/timer circuit System Board
8250 UART
16450 UART
16550 UART with FIFO buffering

Talking about heat - it is also worth noting that the reliability of integrated circuits is directly related to the temperature they run at. While it is not unusual for processors in modern PCs to run at temperatures close to or even above 100 degrees Centigrade, this means that further increases in temperature will severely impact system reliability, as the the processor or other components break down.Now, most of these components are encased in either plastic or ceramic packages, with the pins jutting out the sides and down. These packages should be kept clean: a build-up of dust or fluff will severely (indeed, almost disproportionately) reduce the ability of the packages to dissipate heat and cool the circuit inside. Moral of the story: don't let dust or fluff accumulate inside PCs!

The low power consumption mentioned above gives rise to another problem. Since the MOS transistors present a high resistance to current flow - hence the low power consumption - they do not allow leakage of static electricity through the circuit. Static builds up, until it reaches a high enough voltage level to 'punch through' the semiconductor gates - and on some circuits, this can be as low as 30 volts, since the dimensions of the oxide layers are so small (typically one micron!).

For this reason, MOS circuits should be treated with extreme care. They are normally supplied either in a plastic anti-static tube, or with the pins inserted into some black conductive foam (since the foam is conductive, all the pins must be at the same voltage, hence there can be no damage), and should be left in this packaging until inserted into a circuit.

When inserting a MOS circuit, such as a processor or memory chip, into a PC, follow this procedure: ensure the PC is unplugged from the mains and all peripherals, then remove the cover. Next, take the chip, in its conductive foam, and place it on top of the metal power supply box of the PC, and spread your hands across the chip, the foam and the power supply, This will ensure that you, the chip and the PC are all at the same electrical potential (i.e. voltage) and you can now remove the chip from its foam and if required, gently 'square up' the pins by rocking it against a flat surface (the power supply) before inserting it into the machine.

Another word on packaging: the 8088, 8086, 8087, 80287 and similar processor, memory and logic chips are packaged in what is called DIP (Dual Inline Package) format. This means that the package is a plastic or ceramic rectangle with either 14, 16, 24, 28 or 40 pins arranged down two sides of the package. Notice that the circuit can be inserted into a socket or directly into a circuit board in two different orientations, only one of which is correct, and the wrong orientation will almost certainly cause damage to the component and possibly other circuitry.

The pins are normally number from one to 40, down the left side and up the right side of the circuit. Pin 1, at top left usually, is marked with a dimple, or, on some chips, there is a notch at the top of the chip between pins 1 and 40. Before removing any chip from a board for replacement, note which way round it goes and insert the replacement the same way! When inserting a component such as an 8087 floating point coprocessor, you should see that the empty socket has similar marking, so you know which way the chip should be inserted.

More complex processors, such as the 80286 and 80386 have many more pins, and are typically packaged in 68-pin JEDEC, QIP packages or leadless chip carriers.

The low power consumption of MOS circuits also gives rise to another problem. Because of their high internal resistance, MOS circuits cannot source or sink much current, and this has two consequences: it means that they cannot drive long lengths of wire at speed (or printed circuit board traces) - a few feet is the absolute maximum - and it means that they cannot drive the inputs of many other other devices - we say they have a low fanout.. For this reason, MOS circuits have to be connected to the remainder of the circuitry of the PC through the older TTL (transistor-transistor logic) circuits, which can provide larger currents and drive more devices simultaneously. TTL chips usually have part numbers which start with 74 or 74LS (the LS variant uses low power Schottky diodes). 7400 series TTL chips are usually classed as SSI (small scale integration), although some, such as arithmetic and logic units,( never seen in PC's) reach the heights of MSI (medium scale integration).

The processor actually operates in cycles, which are generated by a clock generator circuit - in the case of a PC, this is usually a chip called an 8284A, which was designed by Intel specifically to match the 8086/88. This chip uses a crystal to oscillate at 14.31818 MHz, which is divided by 3 to give the PC's 4.77 MHz clock rate. In each cycle, the processor performs some internal function - adds values in registers, shifts values, performs logic. Some of these simple functions are actually microcoded instructions which are used to build up more complex operations such as multiplication and division, which, although single instructions, require multiple clock cycles to execute.

Memory Access

The processor communicates with the outside world during bus cycles. The bus is the processor's connection to external circuitry such as memory and input/output ports. In fact, there are three groups of signals on the bus, each of which is sometimes considered as a bus in its own right: the data bus, over which data flows to and from the processor's BIU, the address bus, on which the processor sends out the addresses of memory and I/O ports which it wants to access, and the control/status bus, which carries miscellaneous signals specifying things like whether a memory access is a read or a write, whether it is accessing memory or I/O ports, the time duration over which the address lines are guaranteed to be stable and other miscellaneous signals.

It is important to distinguish this local bus, which allows the processor to communicate with its immediate support circuitry, from the system bus, which is a buffered extension of the local bus, and is used to access peripheral equipment, memory boards and the like. We'll look at the system architecture of the PC in the next article, and you'll see the various buses then.

In a typical bus cycle - say, to read a memory location - the processor will set the address bus to the appropriate values, together with the various status signals to indicate a memory access (as opposed to I/O), a read, and so on. One of the signals indicates that the address is being held steady and is valid. Somewhere else on the bus - say, on a memory board - the address decoding logic recognises the address and turns on the chip select line on a particular memory chip. The chip internally decodes the low-order address bits and copies the value of the corresponding memory cell to its output. In fact, this happens nine times over, for the eight data bits plus parity which make up a memory byte. The nine data bits are then passed through a buffer (which has been enabled by the address decoding logic) and back onto the bus, where, during the next processor clock cycle, the processor reads the data in and responds with a bus cycle acknowledgement signal. The data is then passed, through an internal pipeline or queue, from the BIU to the EU, which will process it, while the BIU fetches the next instruction or data.

Now, as long as the memory is fast enough, all of this will take place at full speed, with no delays. However, processors like the 80386 are so fast that matching memory is extremely expensive - especially in the quantities required by UNIX and OS/2. It is common practice, therefore, for the memory to be slower than the processor. Obviously, if nothing was done about this situation, the processor would attempt to read in data before the memory circuitry has placed it on the bus, and the result would more than likely be a crash.

Hence the need for wait states. Wait states are generated by the processor's support circuitry, and slow it down. As usual, the processor emits the appropriate address and status signals, but then loops around, killing time and doing nothing until the wait state circuitry lets it proceed, by which time the data on the data bus should be stable and valid. Notice that the processor's clock speed remains the same, and its clock cycles are the same - but the bus cycles are slower. Beware, therefore, of comparing systems on the basis of clock speed, because wait states can upset the calculations considerably.

PC System-Level Operation

Apologies in advance for the language in this section (not that it's rude!); the computer industry has done as much as any other to mangle English, and for some readers these few pages will present a severe case of jargon shock. Still, at the end of it, you will be able to amaze your friends and colleagues by bandying around such phrases as wait states, bus contention, cycle-stealing DMA and non-maskable interrupt. More to the point, you should also understand them!

In the meantime, as you read this article, you may want to refer to the accompanying glossary from time to time.

This article should be read in conjunction with Figure 1, which is a block diagram of the original model IBM PC. Each box on the diagram represents a major subsystem of the PC, such as the DMA controller, random access memory or the ROM BIOS. Some of these subsystems are implemented as LSI integrated circuits, and in this case, the box will also carry the component number, such as 8259A (interrupt controller) or 8253 (counter/timer circuit).

As discussed above, the operation of the system really starts with the 8284A clock generator circuit, which provides the 'heartbeat' of the processor and associated circuitry (which is why one really cannot refer to the CPU as the 'heart' of the computer - it is more appropriately referred to as the brain).

The clock is derived from the 14.31818 MHz crystal oscillator. MHz is an abbreviation for megaHertz: mega is, of course, the prefix for million, and Hertz are cycles per second. The clock circuit divides this by three to derive the 4.77 MHz clock signal to the processor and bus. This 4.77 MHz signal is the processor clock cycle, and should not be confused with the bus cycles in which the processor access memory and I/O ports, and which are considerably slower.

Even quite simple processor instructions require multiple clock cycles, and some instructions such as multiply and divide can run into the hundreds of clock cycles. This means that over many clock cycles, the processor is not actually accessing the bus, and this means that other devices can step in and use the bus instead - a point I shall return to later.

Let's look at the way the processor is interfaced, via the bus, to the other circuitry of the PC, before turning our attention to the other processor support circuitry.

Since the processor is an NMOS circuit, as explained above, it can only drive relatively short lengths of cable or bus lines around the printed circuit board. In particular, it has a relatively low fan-out. The fan-out of a circuit is the number of other similar circuits the chip can drive - 10:1 is fairly typical, but an NMOS circuit can drive only a small number of TTL circuits. (Remember that TTL is Transistor Transistor Logic - circuits with a 74 or 74LS part number).

Consequently, the bus signals from the CPU must be buffered through some TTL circuits so that the bus can drive more circuits.

The address bus is purely an output from the CPU - it is never read by the CPU, although other circuits may generate address signals - and consequently the signals simply need to be passed through a single-direction buffer. The various control signals are similarly mostly outputs from the CPU with a few inputs.

However, the data bus is bidirectional; sometimes it is an output from the CPU, as it writes memory locations or I/O ports, and at other times it is an input, as the CPU reads memory or ports. This means that the bus must pass through bidirectional buffers. These buffers function as outputs when required to drive the bus, and as inputs when the CPU wants to read the bus and something else - such as a memory board - is driving the bus.

In particular, when the CPU is not actively controlling the system - as, for example, when the DMA controller is transferring data and the CPU is ignoring this - then it must effectively disconnect itself, so that it does not attempt to drive the bus signals in the opposite direction from the DMA controller. This requires the use of a tri-state buffer, which, as the name, suggests, can be in one of three states: acting as an input, an output, or effectively disconnected from the bus.

Peripheral or expansion boards or sub-assemblies also use MOS circuitry and are similarly buffered from the expansion bus; most of the time, for example, a memory board is not being accessed, and so it is 'tri-stated', effectively disconnected from the bus.

The use of tri-state logic allows the various subassemblies of the machine to operate independently: those which are being addressed will be connected to the bus, while those which are not active effectively 'disappear' and are not involved in the operation of the system.

You can think of tri-state logic as being equivalent to a 'party line'; each device can pick up the phone and replace it, and if the phone is up the device can either talk or listen. Unlike a real phone line, devices cannot talk and listen at the same time; nor can they speak or listen unless specifically directed to do so by the assertion of their address (by either the CPU or some other device).

Another important point which affects the buffer circuitry around the 8088 is that it uses the same pins for both the address and data buses. First, it places the desired address on the bus pins, and this must be latched, or stored, by the address buffer. Once the address has been latched and is being transmitted to the appropriate memory location or I/O port, the same pins are used to transfer data into or out of the CPU.

In fact, the simplest bus cycle consists of four CPU clock cycles which are called T states. During the first T state (T1), the CPU sends out twenty bits of address information, which will be read and latched by the address buffer circuitry. During T2, the processor removes the address data, and either tri-states its address/data pins in readiness to read data, or asserts write data. During T3, the processor will either sample the read data, or continue to assert write data.

T3 may be followed (in some systems) by one or more additional clock cycles called wait states (TW). If the selected memory or I/O device is not capable of transferring data at the maximum CPU transfer rate, then it must signal the CPU 'not ready', which forces the processor to insert wait states. When the selected device has had enough time to complete the transfer, it signals that it is ready, and the processor continues. The processor will latch the data on the bus either during the last wait state, or during T3 if there are no wait states. Finally during T4, the bus cycle is terminated, the command lines are disabled and the selected device deselects from the bus. This avoids problems with bus contention, which is a situation that can arise when a newly-selected device tries to drive the bus before the previous device has deselected.

The wait state logic can be found at the lower left of Figure 1, and connects to the clock generator circuit below the CPU.

So the bus driver circuitry around the CPU performs several functions:

it latches the address from the multiplexed address/data pins of the CPU and separates the signals into separate address, data and control buses

it isolates the processor subassembly from the rest of the machine, and tri-states the processor off the bus when necessary

it buffers the processor signals so it can drive a much larger system, and in particular multiple expansion slots.

Turning now to the processor area, you will find that the majority of machines incorporate an empty socket next to the processor, which will accept an 8087, 80287 or 80387 processor (these couple with the 8086/88, 80286 or 80386 processors respectively). The 80x87 is a floating point coprocessor, which (if fitted) speeds up recalculation of spreadsheets and other floating point-bound applications.

The 8087 sits on the same bus as the main processor, and ignores most of the instructions and data which the 8088 reads. However, the 8088 supports a class of instructions called ESC (escape), which do nothing (or not much) on the 8088 - it mostly ignores them. The 8088 fetches the instruction, but as it does so, the 8087 simultaneously reads it, and if it is meant for the 8087, decodes it and starts executing it. Although the 8088 may not execute the instruction, it will decode the address mode information and, if necessary, fetch any data in the next bus cycle. The 8087 will read this data also and use it.

The two are synchronised by a connection between them, and, since some 8087 instructions can require several hundred clock cycles to execute, the 8088 will on occasions execute a WAIT instruction to wait for the 8087 instruction to complete. The 8087, therefore, is a kind of 'parasitic processor' which depends upon the 8088 to fetch its instructions for it.

While the 8088 can perform integer arithmetic on 16-bit values (between -32767 and +32768) it cannot directly perform arithmetic on larger values. In fact, it has to start performing long multiplication and division by methods similar to those many of us learnt at school (and forgot!). Floating point arithmetic (with decimal fractions like 3.14159, for example) are particularly tricky and slow. The 8087, on the other hand, has a set of eight 80-bit registers which operate rather like a Reverse Polish Notation calculator (such as those made by Hewlett-Packard), and can perform a range of arithmetic, logarithmic and trigonometric operations and functions at between 50 and 100 times the performance of the 8088.

Returning to the system board block diagram, to the right and below the 8087 is a 74LS245 data buffer. This is a bidirectional buffer which connects the processor to the main bus, allowing many more devices to be attached to the processor. Below this is the 8288 Bus Controller. This special-purpose chip connects to the 8088's status pins (which also double as the upper bits of the address bus) and decodes the information presented to generate a more conventional set of control and status signals, such as I/O Read, I/O Write, Memory Read and Memory Write signals. These signals are fed around the system board to the other modules, as well as to the expansion bus and thereby to various plug-in boards.

Moving across to the right half of Figure 1, we come to those other modules. First, at the bottom of the diagram, we find a set of 8K x 8 ROM chips. One of these contains the ROM BIOS for the machine, a set of low level routines which drive the hardware at a very basic level. For example, when the machine is first powered up, the processor is reset, clears its various registers, and then starts execution at address FFFF:0000H. This address is decoded by the ROM CS (Chip Select) decoder circuit, which enables the ROM BIOS ROM, and the lower-order address bits are decoded by the ROM itself to address the individual instructions and data inside the ROM.

The routine starting at FFFF:0000H is the power-on reset routine, which initializes the other circuits in the system by writing the appropriate values into their registers. It then detects any plugged-in boards, and performs diagnostics before booting the operating system, a process we shall look at later.

The other ROM chips are only found on genuine 'true Blue' IBM machines, and contain the Cassette BASIC interpreter.

Of course, the processor does not only execute instructions from ROM, it also runs programs in RAM. The RAM on the PC system board can be found in the upper right of Figure 1. On the very earliest PCs, 16 Kbit chips were used, with one bank only installed on the smallest systems, which could only use cassette tape for mass storage. Plugging in an extra three banks of RAM chips allowed 64 Kbytes of memory, enough to run a disk operating system. Later models used four banks of 64 Kbit chips for 256 Kbytes, while more recently, machines have used 256 Kbit and 1 Mbit chips to provide 512 Kbytes or 1 Mbyte on the system board.

You have probably noticed that the drawing refers to 16K x 9, rather than 16K x 8 as you might expect to make up 16 Kbytes. The extra bit of memory is used for error detection, in the form of parity. This means that if one of the memory chips fails and returns the wrong value the parity check logic circuitry detects this fact and generates a Non-Maskable Interrupt (NMI).

Parity can be either odd or even - I can find no indication in the PC Technical Reference Manual as to which is actually used, but it hardly matters. In essence, in an odd parity system, the parity generation circuitry writes either a one or a zero into the ninth bit of each byte in order to keep the total number of ones in the nine-bit 'byte' an odd number. On reading back the 'byte', if the number of ones is not odd, then one of them must be wrong. This fact is signalled to the CPU by a Non-Maskable Interrupt, which forces the CPU to immediately execute a routine in the ROM BIOS which displays an error message and hangs the machine.

The memory chips - especially high capacity ones like 1 Mbit chips - have so many address bits going into them that, like the CPU, they have to make two signals share one pin. Internally, the memory cells are organised into an array of rows and columns, and so we present the address from the CPU to the memory chip in two halves: the row address and the column address. That's why the memory control logic has two signals running from it called RAS (Row Address Strobe) and CAS (Column Address Strobe), which tell the memory chips just which part of the address they're getting at any particular time. The address multiplexer feeds the two halves of the address to the chips, while the memory buffer interfaces the NMOS memory circuits to the bus, just as for the processor.

So far, so good; we now have a processor which can read instructions from ROM or RAM, read data from both and write back data to RAM. Next we need some form of input/output to allow us to communicate with the machine, and to interface to mass storage devices.

At the simplest level, such interfacing is achieved through I/O ports, which are simply latch circuits which couple to external circuitry. Although the 8088 processor can generate 20 bits of memory address information to access up to 1 Mbyte of memory, none of these addresses is used for I/O ports (unlike the 68000 processor used in the Macintosh, for example, which has no separate addressing for I/O ports). Instead, the 8088 has separate instructions for reading and writing I/O ports (not surprisingly called IN and OUT respectively), and these instructions can address 65536 of each kinds of ports.

So, for example, by loading the DX register with the value 03F8H, and executing the instruction IN AL,DX we could read the last character received by the COM1 port.

The PC has a few I/O ports which are polled directly like this. Referring to Figure 1 again, just to the right of centre you'll find the 8255A-5, a chip which provides either two or three 8-bit I/O ports, depending on how it is set up. In this case, it is used to read the configuration switches, which are a pair of DIP switches set up to indicate, for example, how many floppy disks there are in the system, how much memory, whether an 8087 is plugged in and so on. The AT dispenses with this, replacing it with some permanently powered (low-power) memory which contains the same information.

The 8255A also is used to access the cassette interface (on the original PC only) and the loudspeaker logic (turning the speaker on and off, for example).

The trouble is that, for all but the simplest uses, this is time-wasting and very inefficient. If we are expecting a character to arrive at the serial port, we must be prepared for it, and loop around, checking the status of the port until the RBF (Receive Buffer Full) flag goes high indicating a character has arrived, then read the character as soon as possible to avoid the next character overrunning this one, and finally process the character as quickly as possible to be ready for the next one.

In practice, a lot of time is wasted looping around on the odd chance that a character might arrive, and this is time that could be better spent doing something else. For example, the time-of-day clock has to be updated once a second, and that's a job that can't be done if the CPU is busy waiting for a serial port to come alive.

The solution to this problem is the use of interrupts, which allow the CPU to ignore things like I/O ports until something actually happens. The 8088 and its relatives allow for up to 256 different interrupts with relative simplicity. It's important to distinguish between hardware interrupts and software interrupts, though. Software interrupts arise directly from program execution (e.g. an INT instruction) or indirectly through program logic, such as attempting to divide by zero. Hardware interrupts originate from external logic circuitry. No matter how an interrupt was generated, the result is the same: the processor calls the corresponding interrupt service routine, either in the ROM BIOS or in the operating system. For the first part of this discussion, I'll deal with the hardware only.

Hardware-originated interrupts are classified as either non-maskable or maskable. Maskable means that, by setting a flag in the processor registers, the programmer can cause the processor to ignore or 'mask out' interrupts. This is important, especially when actually servicing interrupts, when further interrupts can 'over-run' the processor, or when executing certain critical sections of code. A non-maskable interrupt, however, cannot be ignored; it is usually used to ensure a fast response to error conditions such as a memory parity error or power failure (on some systems, it is just possible for the processor to save its current status into some form of non-volatile storage before the power decays completely).

The non-maskable interrupt is triggered by an input signal pin on the processor, which as you can see from the system block diagram, is generated from the NMI logic circuitry which combines signals from the memory parity circuitry, I/O circuitry and the numeric processor. Maskable interrupts are also triggered by another pin (INTR - interrupt request).

I mentioned above that the 8088 can handle 256 interrupts with no fuss and no mess - how can this be done with just two pins? Enter the software side of interrupts. The bottom 1 Kbyte of memory is reserved for the Interrupt Vector Table (actually the 80286 processor used in the AT and PS/2's can put the IVT anywhere). Since an address on the 8086 family processors comprises a 16-bit segment address and a 16-bit offset (i.e. an address occupies four bytes) the interrupt vector table can contain 256 entries, each of which is the address of the entry point of the corresponding interrupt service routine (ISR).

Certain interrupts are dedicated to specific functions by Intel. For example, attempting to divide by zero immediately causes the processor to generate interrupt zero internally, and it will therefore pick up the address in the first (zeroth?) entry in the interrupt vector table and CALL the routine at that address (which prints 'Divide by zero overflow' and returns you to DOS. So now you know. . .).

Likewise, interrupt 1 is reserved for single-stepping through programs while debugging and interrupt 3 is used to set breakpoints in programs, again in debuggers. Interrupt 4 is used to respond to overflows in arithmetic. Interrupt 2 is the NMI interrupt vector, which means that whenever the NMI input to the processor goes positive for more than two clock cycles, it breaks off from what it was doing, picks up the address in entry 2 of the interrupt vectors, executes that subroutine and then resumes where it left off.

Notice that the interrupt service routines themselves are not in the interrupt vector table; they are elsewhere and the entries in the table say where. Also notice that the interrupt vector table is in RAM, at the bottom end of memory, and not in ROM, so one of the first jobs the ROM BIOS has to do is to place the correct entries in the table.

Of course, more than the five situations I have described above can arise in a processor, especially a more powerful one like the 80286 or 80386. Intel therefore reserved the first 32 interrupt vectors for future use, but you've guessed it - IBM and Microsoft went ahead and used them anyway. For example, on the 80286, interrupt vector 5 is triggered whenever an array subscript goes outside the bounds of the array. However, IBM used interrupt vector 5 to hold the address of the 'PrtScrn' screen dump routine, which led to the not-so-humorous situation of slightly errant programs dumping their screens - again, and again, and again. . .

Fortunately, this situation has been fixed in the offending programs, but it illustrates the problems that can arise when designers don't pay attention.

The interrupt vector table provides a way of addressing 256 different interrupt service routines, but how do we know which one to use to service an interrupt when the INTR line goes off?

In theory, the processor could handle multiple interrupts by having a single interrupt service routine which polls the various peripherals (by reading their I/O ports) to see which one requires service and then branches to the appropriate handling routine. But this is slow, and the polling routine would have to be rewritten every time a new peripheral card is added. It is much easier, faster and more flexible to provide the processor with some hardware assistance in the form of a programmable interrupt controller chip.
In the case of IBM-style PCS, this chip is an Intel 8259A or compatible; in many machines the 8259A functionality is actually embedded in a multi-chip set such as the NEAT chipset.

The 8259A has eight inputs for the various interrupt signals. It assigns a priority to each, and when an interrupt occurs, it works out whether that interrupt should be able to override an existing interrupt or should wait until the current ISR has completed. It can also rotate priorities so that each interrupting device gets a 'fair share' of processor response, and can also mask out particular interrupt inputs so that they are ignored.

An IRQ is one of the lines which feeds into the 8259A interrupt controller. Because the IRQ signals are generated by peripheral cards when they need the processor to respond urgently, they are communicated from the cards to the interrupt controller via the machine's expansion bus.

AT-class or ISA machines may have a need to deal with more expansion devices: multiple disk controllers or network cards, for instance. So an AT-style machine has two 8259A chips (or equivalent circuitry) with the output of one of the PIC's feeding into the IRQ2 input of the next. Accordingly, an AT is able to handle 15 IRQ lines while an XT can handle only eight.

When a device signals an interrupt on the bus, it does so by asserting (driving high [to 5V]) one of the IRQ lines. This pulls high the corresponding input to the 8259A, and (in ISA machines) the transition from a zero to a one signals the interrupt. The 8259A will assess the priority of the interrupt, and if it is the highest priority interrupt currently asserted, it will enter the next stage of processing.

The 8259A now sends an interrupt to the processor on its INT line, and the processor (8088 or 80286/80386) responds with an interrupt acknowledge signal. The 8259A now sets an internal signal to indicate it is servicing the interrupt and resets the interrupt request bit. Now the processor emits a second interrupt acknowledge signal. This is the sign for the 8259A to release an eight-bit number onto the processor data bus. This eight-bit number is the number of the interrupt vector which points to the interrupt service routine.

The 8259A is programmed to generate a number which is eight higher than the actual IRQ number. This is because the first few interrupt vectors are allocated to error condition traps or debugging interrupts in the CPU itself. IRQ 0 therefore translates to interrupt vector 8, and on receipt of IRQ 0, the processor will therefore CALL the ISR at location (8 * 4 =) 0000:0020H.

On AT-type machines, the second 8259A is programmed to generate an interrupt vector in the range 70H - 77H. Notice also that because the second PIC daisy-chains to the first through its IRQ 2 input, all the second-tier interrupts (IRQ 8 - IRQ 15) come between IRQ 1 and IRQ 3 in priority.

It is possible for programs to change the interrupt vector table entries around, for example, to intercept keystrokes before the operating system has had a chance to process them. This technique is called {italics} hooking interrupt vectors, and it is commonly used by TSR (terminate and stay resident) utilities which are activated by a hot-key combination, such as Sidekick.

When adding a new card to a PC - for example, a network interface card - it is important to know which interrupts the system currently uses and which are free to be used by the new card. Most cards have some movable links which can be used to set the interrupt which the card will generate. The majority of (particularly low-cost) network cards only allow generation of (some of) interrupts 2 - 5, and a machine with a number of these boards may run out of assignable interrupts. This is one of the main reasons for buying AT-specific cards - they usually allow assignment of interrupts 8 - 15.

PS/2 MCA (MicroChannel Architecture) machines have always had all 15 interrupts available, so MCA cards usually have fewer clashes. Notice also that MCA (and EISA) use level-triggered interrupts, rather than the edge-triggered interrupts described above. This makes it easier for multiple devices to share a single interrupt (e.g. COM1 and COM3).

Priority Integer Description

1 NMI Parity Error, Channel Check, System Watchdog Timer
2 IRQ 0 Periodic interrupt - system tick - from CTC Channel 1
3 IRQ 1 Keyboard input interrupt
IRQ 2 Daisy Chain from Second 8259A
4 IRQ 8 Real-time clock chip
5 IRQ 9 Expansion bus
6 IRQ 10 Expansion bus
7 IRQ 11 Expansion bus
8 IRQ 12 Expansion bus
9 IRQ 13 80287 coprocessor
10 IRQ 14 Fixed disk drive controller and expansion bus
11 IRQ 15 Expansion Bus
12 IRQ 3 COM2 port and expansion bus
13 IRQ 4 COM1 port and expansion bus
14 IRQ 5 Parallel port 2 and expansion bus
15 IRQ 6 Diskette drive controller and expansion bus
16 IRQ 7 Parallel port 1 and expansion bus
Table 1. Hardware Interrupt Lines

INT 0H Divide by Zero Overflow (CPU)
INT 1H Single Step Interrupt (CPU)
INT 2H Non-maskable Interrupt (CPU)
INT 3H One-Byte Interrupt Instruction (Software breakpoint) (CPU)
INT 4H Interrupt on Overflow (CPU)
INT 5H Screen dump routine (HW) Array subscript bound exceeded (CPU)
INT 6H Invalid opcode (CPU)
INT 7H Coprocessor not available (CPU)
INT 8H IRQ 0 (HW) Double Fault Error (CPU)
INT 9H IRQ 1 (HW) Coprocessor Segment overrun (CPU)
INT AH IRQ 2 (HW) Invalid Task State Segment (CPU)
INT BH IRQ 3 (HW) Segment Not Present (CPU)
INT CH IRQ 4 (HW) Stack Segment Overflow (CPU)
INT DH IRQ 5 (HW) General Protection Fault (CPU)
INT EH IRQ 6 (HW) Page Fault (CPU)
INT FH IRQ 7 (HW)
INT 10H Video I/O (BIOS)
INT 11H Configuration (BIOS)
INT 12H Base Memory Size (BIOS)
INT 13H Disk Drive I/O (BIOS)
INT 14H Serial Port I/O (BIOS)
INT 15H BIOS Extension (BIOS)
INT 16H Keyboard I/O (BIOS)
INT 17H Printer I/O (BIOS)
INT 18H Bootstrap Fail (BIOS)
INT 19H Bootstrap (BIOS)
INT 1AH System Tick / RTC (BIOS)
INT 1BH Control-break Service (DOS)
INT 1CH Tick Counter Service (DOS)
INT 1DH Video Parameter Table Address (BIOS)
INT 1EH Diskette Parameter Table (BIOS)
INT 1FH Extended Graphics Character Set (DOS)
INT 70H IRQ 8 (HW)
INT 71H IRQ 9 (HW)
INT 72H IRQ 10 (HW)
INT 73H IRQ 11 (HW)
INT 74H IRQ 12 (HW)
INT 75H IRQ 13 (HW)
INT 76H IRQ 14 (HW)
INT 77H IRQ 15 (HW)
Table 2. Interrupt Vector Table Entries

Notes:

(CPU): Interrupt generated within the CPU itself in response to error or debugging or virtual memory condition.

(HW): Interrupt generated by external hardware. See corresponding IRQ table for likely source.

(BIOS): Entry point into ROM BIOS

(DOS): Used by MS-DOS/PC DOS.

When the INTR input goes high, the 8088 responds by two interrupt acknowledge bus cycles. During the first, it sends a LOCK signal to the 8288 bus controller, which locks out all other devices from interfering with what happens next. In response to the second interrupt acknowledge bus cycle, the 8259A interrupt controller places a byte on the data bus which identifies the interrupt number or type (being an 8-bit byte, this accounts for the restriction of 256 interrupts). The processor reads this byte and multiplies it by four, which provides the required index into the interrupt vector table. It then saves the machine status by pushing the current contents of the flags register onto the stack and clears the interrupt enable and trap flags, to disable subsequent interrupts. Finally, it saves the current CS and IP register contents (i.e. the return address) onto the stack and then calls the interrupt service routine.

The 8259A works out what interrupt vector number to place on the bus from two things: first, how it was programmed (by the ROM BIOS) and second, which one of its eight inputs was driven by the interrupting circuitry. In fact, it is possible to implement up to 64 hardware interrupts by cascading the outputs of eight 8259A's into a ninth. Although this would be unusual, the AT combines two 8259A's to provide up to 15 hardware interrupts.

The 8259A is so complex for two reasons. The first, which need not concern us directly, is that Intel designed it to work with the earlier 8-bit processors as well as the 8086/88 family. Secondly, there's the problem of prioritizing interrupts (I did apologize earlier for the language, didn't I?).

In a typical PC or indeed, any other microprocessor-based circuit, multiple events will occur to trigger interrupts. The system clock ticks, floppy disk transfers complete, hard disk transfers complete, packets arrive across a network, the user presses keys on the keyboard, characters arrive on the serial ports, the video circuitry signals it is now retracing and it's OK to update screen memory - the list goes on and on. The question is, if the processor is busy servicing a keyboard interrupt and the disk system interrupts, should that interrupt take precedence or should it wait until the keystroke has been read? Answer: if another disk transfer is likely to immediately follow this one, then we had darned well better service the disk interrupt and clear the disk buffer, otherwise the next sector to be read will overwrite this one.

The designer of a computer has to construct a hierarchy of interrupts, specifying which ones get priority and which don't. Furthermore, additional hardware plugged into the system has to slot into this hierarchy in the appropriate position, and the operating system also has to fit in and manage all of this.

The 8259A contains special programmable circuitry which automatically takes care of the prioritizing of interrupts, and will allow interrupts to be nested or force them to be serviced one after another. If you ever really need to know about the internals of the 8259A (if you're writing interrupt-driven communications software, for example, you'll need the appropriate data sheets as well as Intel's Application Note AP-59, "Using the 8259A Programmable Interrupt Controller", a neat little 40-page introduction to a chip that has probably provided a full career for some programmers. Incidentally, the book "Systems Software Tools" by Ted J. Biggerstaff provides a somewhat lighter introduction to the 8259A as well as other aspects of PC systems programming.

Just right of center on the block diagram you can see the 8253-5 counter/timer circuit. This chip has three counter/timer channels, which fulfil several functions in the PC. First, channel 2 is used to generate tones which drive the loudspeaker (one port on the 8255A can turn the tone on and off). This is where the various beeps your PC issues come from. Secondly, channel 1 is used to provide the system tick. Under DOS, this channel counts down to zero and provides an interrupt (IRQ 0) 18.2 times per second. Notice that although this signal connects to the IRQ 0 input on the 8259A, this is not the same thing as interrupt zero (the divide-by-zero interrupt). In fact, it uses entry 8 in the interrupt vector table.

Likewise, the keyboard logic connects to IRQ 1 on the 8259A, but actually corresponds to interrupt 9 in the table. This interrupt is triggered each time the user presses (or releases) a key, and the corresponding interrupt service routine reads the keyboard and places the character in a buffer where it will be read later by the operating system. This is how you are able to type ahead 16 characters on the PC.

While two of the 8259A IRQ pins are dedicated on the system board, the other six are bussed to the expansion connectors for use by add-on boards such as disk controllers.

Returning briefly to the 8253, the last channel (channel 0) is used to time and request refresh cycles from the DMA controller - of which more later. The reason for this is that PC's typically use dynamic memory, as opposed to static memory. Static memory cells typically use three transistors, but as long as power is applied, the cell will maintain its contents - a one or a zero. Dynamic memory cells, on the other hand, use a single transistor, and being smaller, allow more storage on a given size of circuit, which is their main attraction. The drawback is, though, that the contents of a dynamic RAM cell gradually fade away unless the cell is written to. When I say gradually, I mean that the cell will lose its contents if not rewritten - we say, refreshed - every two milliseconds, which is done by reading every cell.

Special circuitry on the RAM chip performs this refresh, but it still needs every cell on the chip to be addressed every two milliseconds at least, and this chore is performed by external refresh circuitry. Although semiconductor manufacturers have designed and produced self-refreshing memory chips, they are so big and so expensive that they are not popular.

In the case of the PC, refresh is performed by a chip called the DMA controller, although that is not its principal function.

DMA

When a disk controller reads a sector off a disk, the sector is read directly into the memory on board the disk controller board, not into main memory. It must now be transferred into main memory, a process that can be achieved in one of two major ways: programmed I/O transfers or DMA (direct memory access).

In programmed transfers, the processor enters a very tight loop, first reading a byte from the disk controller (possibly from an I/O port) into an accumulator and then writing that byte out to the approriate memory location. This technique is limited by the processor performance, and is further restricted by the fact that for each bus cycle that transfers data, there are several bus cycles fetching instructions from memory. Plus each data transfer requires two cycles - one in, one out to memory.

Direct Memory Access (DMA) is a higher performance technique which uses special circuitry, rather than the processor, to generate addresses as the destination of write commands. The DMA circuitry of the PC is based on the Intel 8237A DMA controller chip. This chip has four channels, only one of which is used on the system board of the PC.

The counter timer circuit (8253) is programmed to periodically request a dummy DMA transfer, which creates memory read cycles independently of where the CPU is addressing, thereby periodically refreshing the memory chips. Incidentally, this works not only for the RAM on the system board, but also on expannsion boards also - at least, those that fall within the address space of the processor, which excludes RAM on expanded memory boards.

The remaining three channels on the DMA chip are available for use by expansion cards. Devices which use DMA channels are floppy disk controllers, tape drives, and network interface cards. In all cases, DMA channels are used to provide rapid data transfer to and from memory.

As we have seen the 8088 can address up to 1 Mbyte, which requires 20 bits of address information, but the 8237 DMA channels only generate 16-bit addresses. The solution adopted by the designers of the PC (rather than use Intel's more expensive 8089 DMA Processor chip) was to use a latch circuit to hold the upper four bits of address information.

The DMA controller will automatically cycle through up to 64 Kbytes of memory, but when it reaches a 64 Kbyte boundary it goes back to zero and the latch must be explicitly reset by the processor. This gives rise to problems while DOS is booting, if a device driver loaded from CONFIG.SYS spans a 64 Kbyte boundary. The solution is to change the order of the DEVICE= statements in CONFIG.SYS. This is not a problem once DOS is up and running, as DOS splits transfers over a 64 Kbyte boundary into two separate transfers, with the latch being reset between them.

Notice that although DMA is used by a variety of devices, none of them is actually on the system board. Virtually all of the I/O devices for the PC are on plug-in cards as options, and so we have not yet covered the operation of the video adapters, disk controllers and other options. Notice that although a typical system has four DMA channels - two of them spare - there is no 'standard' which defines which channel should be used for tape drives and which for network cards. It is therefore not unusual to buy a network card and a tape controller and discover that they won't work together because they both try to use the same DMA channel.

The optional cards plug in to the expansion bus, which is shown at center right. Although the original PC had only five slots, most modern machines have eight.

Although this guided tour through the circuitry of a machine has used the original IBM PC as an example, all of what we have discussed applies to the PC/AT as well - and also AT-compatible 80386-based machines. The major differences are that the AT dispenses with the configuration switches, storing its configuration information in battery backed-up low-power RAM. The same RAM chip also contains a real-time clock circuit, so that the machine tracks time, even when it is switched off.

As mentioned, the AT has two 8259A interrupt controllers, and also two 8237A DMA controller chips. Furthermore, because the 80286 processor used in the AT can address 16 Mbytes of memory, the DMA Address Latch holds an additional 8 bits of data, rather than four. Otherwise, for compatibility reasons, the circuitry of an AT-type machine is functionally, if not physically, identical to that of a PC or XT.

More modern machines often do not have the specific integrated circuits shown here. For example, the Compaq Portable 386 has the equivalent of two 8237 chips and more built into s single ASIC (Application Specific Integrated Circuit). Most new machines these days are based on ASICs, such as those made by Chips and Technologies Inc, which put all the functionality of an AT into a handful of chips.

The PS/2's

Unlike older PC's, the IBM PS/2 range put a lot more input/output circuitry on the main system board, including a parallel and a serial port and the VGA (Video Graphics Array). Another important difference in the new machines is that the Technical Reference Manual no longer includes full circuit diagrams and the ROM BIOS listings, so we cannot provide as full an analysis of the PS/2 range. however, functionally, much of the PS/2 circuitry is the same as for earlier AT's - it has to be for the same software to run.

Here is a block diagram which shows the circuitry of the PS/2 Models 50 and 60 in outline form. At the heart of the system is the 80286 processor, which as you can see, is supported by an optional 80287 floating point coprocessor, and an eight-channel DMA controller circuit. These three circuits form the kernel of the system, and run on their own bus, which is isolated from the rest of the system - and particularly the expansion connectors - by a set of buffers. Once again, the bus can be logically divided into three 'sub-busses' for address, control and data signals.

The PS/2 memory is treated as a separate subassembly, buffered from the rest of the system, and with its own control circuitry for refresh. Notice, too, that standard RAM is now 1 Mbyte: one of the functions of the address control circuitry is to decode the processor's address lines in such a way that 640 Kbytes of that megabyte appears as the bottom 640 Kbytes to the processor, but the remaining 384 Kbytes is displaced, to appear above 1 Mbyte so that it does not conflict with the ROM BIOS and VGA, which map between 640 K and 1 Mbyte. Finally, you'll see that the ROM has increased in size from 32 Kbytes to 128 Kbytes - this is because it contains two BIOS's: a conventional one for DOS and the ABIOS (Advanced BIOS) which is used by OS/2.

The remainder of the system board circuitry is also connected to the Microchannel Architecture bus via a buffer. As for the PC and AT, there is a 3 channel timer and a 16-level interrupt controller, which is compatible with a pair of 8259A chips., but also on the system board is a parallel port (similar to the 8255A on the PC, though for a different purpose - driving a printer), an RS-232C serial port, and a keyboard and pointing device control port. Finally, two other modules are normally separate boards on older machines: the VGA video graphics array and the diskette controller. However, the fixed disk adapter is still a separate board, in order to accomodate a range of models and requirements for field upgrades of hard disk capacity.

To the left of this diagram, you can see some special circuitry in the form of the bus control circuitry, which interfaces the processor bus to the Micro Channel, and the central arbitration point. This feature allows multiple processors to share the MCA bus, as peers. It also means that the processor can selectively enable individual boards on the bus, in order to indentify them and configure the system.

At the top right of the PC system board diagram you will find a representation of the PC's five expansion connectors. Essentially, the various data, address and control buses are simply extended in parallel through a set of connectors. In the PX and XT all the coneectors are identical and boards can generally be plugged in anywhere.

Now, the AT uses the 80286 processor. As previously discussed, the 8088 processor has a 20-bit address bus and an eight-bit data bus, but the 80286 has 24 bits of address and a 16-bit data bus. In order to accomodate older boards, the AT therefore adds an extra connector in front of the original, which carries the additional address and data bits. An older board will still plug in, but will not connect with the front connector, so that it is still accessed in eight-bit bytes rather than 16-bit words and it can only decode the bottom 20 bits of address information. Boards made for the AT on the other hand, will plug into both connectors and be fully functional. A similar scheme is used to allow the EISA bus to support 16-bit and 32-bit boards.

The memory on the system board varies in size; on the original PC it was 16 KB expandable to 64 KB on-board, while later machines expanded this to 256 KB, 512 KB and 1MB. The most important point is that the memory can extend up to 640 KB, leaving the space between 640 KB (A0000H) and 1 MB (FFFFFH) inclusive to be available to expansion cards. Let's turn now to those cards.

Graphics Adapters

The first and most important from many perspectives is the video board - after all, with no display it will be hard to work with the machine. At the time of introduction, IBM produced two video boards for the PC - the MDA (Monochrome Display Adapter) and the CGA (Colour Graphics Adapter). The two are similar in basic concepts, but vary in detail. Since then they have been joined (and to some extent replaced) by the EGA (Enhanced Graphics Adapter) and the VGA (Video Graphics Array). Another IBM graphics subsystem, MCGA (Multi Color Graphics Array34) was only used on the low-end PS/2 family and has not been accepted by the market.

Other manufacturers have introduced graphics cards with different formats but rarely met with widespread success - the major exception being the Hercules card, which allows the IBM monochrome monitor to display graphics, in higher resolution than the competitive CGA. Manufacturers such as Plantronics, Matrox, Tektronix and others produce high-resolution graphics cards which, while not achieving mass-market adoption, are significant in the CAD/CAM market.

MDA

The Monochrome Display Adapter was developed to meet the need for a high-resolution, monochrome, non-graphics (text-only), low-cost display. The IBM MDA board also carries a parallel printer port, so that no other slots are consumed to interface to the printer.

The board is based around the Motorola MC6845 CRT (Cathode Ray Tube) Controller integrated circuit, and the functionality of this chip in fact forms the basis for later designs because of compatibility requirements.

The attached figure shows a block diagram of the MDA. At the left side of the drawing are the connections to the PC data bus; the address bus, the data bus and timing signals. Not shown is some address decoding circuitry which is used to select the board memory and in particular the 6845 registers.

At the hardware level, the processor is able to display characters onto the screen by writing them into the MDA's display memory, which is located at address B0000H. This location corresponds to the top left hand corner of the screen, location B0002H is the next character, and so on. Processor writes to the video memory are through an address multiplexer, which allows both the processor and the CRT controller to address the RAM, and through some data bus gating logic. This logic allows the processor to both read and write the RAM and the CRT controller.

Since the screen has an 80 x 25 format, 2 KB of memory is enough to store an entire screenful of text. A second 2KB is supplied to store attribute information, and although only a limited set of attributes are supported, in order to provide compatibility with the CGA, a full eight bits are supported. Each character is stored as a two-byte pair, with the first byte being the extended ASCII code for the character and the scond byte being the attribute information.

MDA Attribute Byte - located at odd bytes interleaved with characters

This diagram shows the content of each attribute byte. The foreground and background bit fields have the following permissible values:

Background Foreground Function
R G B R G B
0 0 0 0 0 0 Non-display
0 0 0 0 0 1 Underline
0 0 0 1 1 1 White character / black background
1 1 1 0 0 0 Reverse video

The CRT controller chip generates the various clock signals which control the MDA, and cycles through the memory addresses continuously, in time with the video scan.

The electron beam scans across and down the screen.

Each character is made up from a 7 x 9 dot matrix, which is contained within a 9 x 14 character box. As the electron beam scans its way down the face of the CRT, so the CRT controller chip increments a counter which addresses the character generator ROM to extract the data for that row of the appropriate character. These are the Row Address signals shown on the block diagram between the CRT controller and the character generator.

The other address for the character generator ROM is the ASCII character being drawn, which comes from an octal (8-bit) latch which captured the character from the MDA memory on the character clock pulse. So the four bits of row address plus eight bits of ASCII character together give us twelve bits of address information, which will address one byte in the character generator ROM which specifies which bits are turned on or off to generate that row of the character. These seven bits (it's a 7 x 9 matrix) are latched into a shift register and then each one, in turn, is fed into the video processing logic, which will apply further processing of attributes as described above.

The characters are formed from a dot matrix.

The attribute information is extracted from RAM, latched and passed to the video process logic through a similar scheme.

The end result is our video signal, plus an accompanying intensity signal (brightens a pixel) and horizontal horizontal and vertical sync signals which tell the monitor when to start each horizontal scan line and each vertical scan respectively.

MDA interface and pinout

CGA

The CGA is basically similar to the MDA in principle, but it varies considerably in detail. It has two basic modes of operation; alphanumeric and what IBM terms All Points Addressable (APA) but is generally known as graphics mode.

In order to meet the needs of the home computer market, IBM designed the CGA to support an alphanumeric 40 x 25 mode. By displaying only forty characters per line, the dot clock frequency can be halved, and is low enough to pass through the restricted bandwidth of a color TV set, particularly when used with an RF modulator. For this reason, the CGA has an NTSC composite video output as well as the now more commonly used TTL video output.

Unlike the MDA, the CGA's characters are defined as a 7 x 7 dot matrix in an 8 x 8 character box, with only one line of descender for lower case. In black and white character mode, the reverse video, blinking and high-intensity modes are available, but the CGA does not have underlining - to get this effect the display must actually be in graphics mode. In color character mode, there are 16 foreground colors and 8 background colors per character, as well as blinking (see Figure 2, which also applies to the CGA). In addition, the border color can also be set.

The CGA board has 16 KBytes of memory - since a 40 x 25 screen requires only 2 KBytes of memory, the 16 KB can be used as eight video pages and the display switched between them. For 80 x 25 displays, there are four video pages.

When switched into graphics mode, the CGA has two resolutions available: 320 x 200 and 640 x 200.

In 320 x 200 mode, each pixel can either be the background colour (any of the sixteen possible) or it can be one of three colours chosen from one of three palettes: Green, Red, Yellow; Cyan, Violet, White; or Cyan, Red, White. In 640 x 200 mode, there is only one bit per pixel on the screen, so the pixel can be either black or a colour selected by the CGA color select register (99% of the time: white).

The system block diagram for the CGA looks very similar to the MDA, with the addition of a graphics shift register which will accept data directly from the video RAM (rather than via the character generator ROM), and colour encoding circuitry which produces the Red, Green, Blue and Intensity outputs.

Its connector interface is shown below, and as you can see, it is also very similar to the MDA.

Enhanced Graphics Adapter

The EGA (Enhanced Graphics Adapter) was introduced by IBM at approximately the same time as the AT computer. While stil able to support the modes of operation of the older CGA, the EGA added a few more modes of its own:

640 x 350, 4-color (black, white, bright and blink) graphics on the monochrome display

320 x 200 and 640 x 200, 16-color graphics on standard IRGB (Intensity/Red/Green/Blue) displays

640 x 350, 16-colour graphics on the IBM Enhanced Color Display (or compatibles such as the NEC Multisync)

Other enhancements include:

a programmable color palette which allows any color attribute to be mapped to any one of 16 colours on IRGB displays and 64 on the ECD

a RAM-based character generator which supports up to 512 different characters

BIOS support for up to 43-line text displays

smooth horizontal and vertical scrolling

hardware support for split displays

hardware support for fast, flicker-free display updates

But this raises another problem: the computer's ROM BIOS contains code to drive the MDA and the CGA, but it does not contain EGA driver code, since the EGA was designed later. How can this work? The answer is that EGA (and VGA) cards carry their own ROM BIOS chip code (at address C0000H), which replaces the video interface in the machine. Exactly how this is done, we shall see in a later article on the ROM BIOS.

Because the EGA provides its own ROM BIOS, when it is installed in a PC or XT the motherboard switches should be set for no display, in order to disable the MDA/CGA routines. The EGA (and VGA) can coexist with an MDA, but in this case, the switch settings should still be for no display.

Video Graphics Array

The VGA (Video Graphics Array) was introduced in April 1987 as a built-in video controller on the PS/2 range system board. At the same time, it was made available as a plug-in board for the old XT/AT bus, and shortly thereafter, third-party VGA boards started to make their appearance.

The VGA adds some more operating modes, as shown in the accompanying table, most particularly the new 640 x 480 graphics modes. Other enhancements include:

the use of a 9 x 16 dot matrix character set

the use of analog RGB video signals, rather than the TTL digital signals which the earlier adapters use. This allows the display of 256,000 different colours (although not all displayable simultaneously with current video cards).

ability to operate with an additional graphics card, the 8514A, to generate up to 1024 x 768 graphics

Some of the older third-party VGA boards were based around a reprogrammed EGA chipset with a revised ROM BIOS, and while that will work OK for programs which do not access registers, it fails badly for those that do. At least one manufacturer, on being informed that OS/2 would not run on their VGA, stated that a 'revised ROM BIOS would cure the problem'. Since OS/2 does not access the ROM BIOS, this would (and indeed did) have no effect. That manufacturer has since released a new range of VGA cards which apparently are hardware-compatible, and the furore over the earlier model has since died away. Caveat Emptor.

The VGA - monitor interface is shown in below.

Many third-party VGA cards have introduced additional modes; the most popular is 800 x 600, for which a standard (of sorts) appears to be emerging.

Display Type
Pin I/O Output Monochrome Colour
1 O Red No Pin Red
2 O Green Mono Green
3 O Blue No Pin Blue
4 NA Reserved No Pin No Pin
5 NA Digital G Self Test Self Test
6 NA Red Rtn Key Pin Red Rtn
7 NA Green Rtn Mono Rtn Green Rtn
8 NA Blue Rtn No Pin Blue Rtn
9 NA Plug No Pin No Pin
10 NA Digital G Digital G Digital G
11 NA Reserved No Pin Digital G
12 NA Reserved Digital G No Pin
13 O Hsync Hsync Hsync
14 O Vsync Vsync Vsync
15 NA Reserved No Pin No Pin

Red Rtn, Green Rtn and Blue Rtn are Analogue Grounds
Digital G = digital ground for sync returns and self test.

Floppy Disk Controllers

The floppy disk got its start as a mainframe peripheral, generally used as a fast way of loading diagnostic programs for field service. In 1974 John Torode and Gary Kildall built the first microcomputer floppy disk controller and operating system respectively, based upon an early 8-inch floppy disk drive from Shugart Associates.

The 8-inch drive soon proved to be too cumbersome for new, rapidly-shrinking PCs and Shugart Associates introduced the 5 1/4" floppy disk drive which soon emerged as the standard for data and program interchange under MS-DOS. 3 1/2" drives are gradually taking over as an emerging standard.

A floppy disk drive operates by encoding data in the form of tracks and sectors onto a magnetic disk . Eight inch disks typically had 77 tracks of 26 sectors each, and since each sector contained 128 bytes, this gave a capacity of 256,256 bytes (less reserved space for bootstrap loader, operating system and directory). By using a double-sided drive, the capacity could be doubled.

The data is not simply written onto the disk as direct data in binary form. Instead, it is written out using a technique called frequency modulation (FM). It did not take long before someone worked out a technique called modified frequency modulation (MFM) which puts twice the amount of data into a single sector, and this quickly came to be known as double density operation.

In the FM technique, a train of zeros is written as a certain frequency and ones at double that frequency. In fact, a bit cell for a zero contains a single flux transition, while a one bit cell contains two flux transitions. Since each cell contains at least one flux transition at the beginning of the cell, the read electronics is able to distinguish the cells easily.

MFM encoding records a single flux transition for a one and no transitions for a zero, but it is a little more difficult for the read electronics to extract the data.

In the eight-inch disk world, double density disks either had 77 tracks and 26 sectors of 256 bytes each (for a double-sided capacity of just over 1 MB) or 77 tracks, each with eight 1 KByte sectors, for approximately 1.2 MBytes double-sided capacity.

For the 5 1/4" drives which are most common today, the dominant format is double-sided, 40 tracks, 9 sectors per track, 512 bytes per sector for approximately 360 KBytes capacity. Other common formats are shown in the table.

# Sides Sectors/ FAT Size Dir Dir Sectors/
Track Sectors Sectors Entries Cluster
1 8 1 4 64 1
2 8 1 7 112 2
1 9 2 4 64 1
2 9 2 7 112 2
2 15 7 14 224 1

MS-DOS 5 1/4" Formats

Since 5 1/4" drives use MFM encoding, they are already 'double density' and so the term, when applied to such drives, is almost devoid of meaning. However, it is possible to achieve higher capacity on 5 1/4" drives by either increasing the number of tracks supported, or increasing the number of sectors per track.

The standard 5 1/4" drive used in the PC and XT moves its read/write heads in increments of 1/48", so that 40 tracks are written in a space somewhat less than an inch. An AT-style drive, however, spaces the tracks at 1/96", so that it can support 80 tracks in the same space. Of course, by skipping every second track, such a drive can still read disks written on an XT - with restrictions (see box).

The disk drives are controlled by, and data written to and read from them by, a disk controller card in the PC. Actually, the PC and XT have separate controllers for floppy and hard disks while the AT combines them, but these days with so many third party PCs, drives and controllers, it is quite common to see AT-type machines with separate drive controllers.

The floppy controller circuit is based upon a single chip floppy disk controller, the NEC µPD765 or equivalent, which does most of the work and requires relatively few support circuits. The floppy disk controller card occupies one of the system board expansion slots, and interfaces to the drive(s) via a 34-wire ribbon-cable (usually grey with one red edge) which has a single connector at one end for the controller card and two connectors at the other for the two drives. It is quite usual for a single-floppy PC to have a cable with two connectors, one unused.

If you compare the two drives in a dual-floppy PC, looking at the printed circuit board from above, you will find that one of them seems to have a component missing. This is quite correct: because the disk controller drives quite a long cable, it could run into trouble with signals being reflected back from the end of the cable. For that reason, the last drive on the cable is fitted with a termination resistor pack to provide the correct impedance at the end of the cable, and this is usually drive A:. Drive B: should have any termination resistor pack removed prior to installation, and the drives should be cabled in such a way that A: is the last drive.

In addition, if you look at the drive cable between the drive connectors, you will probably see that it has been carefully split into three sections and the middle section twisted around. Again, this is quite correct. The part that is twisted should be pins 10 to 16 inclusive, and if you look at Figure 2 you should see that this swaps over the motor enable and drive select pins so that each drive will be correctly enabled even though the drives are wired identically on their circuit boards. This twist ensures that the drive at the end of the cable will always be the A: drive.

The controller chip does most of the work automatically. It responds to 15 different commands. T_he driving software transfers the command and all related data into the 765's registers, waits, and then reads back the result data from the register. Notice that the result data is usually the status of the system following the command, together with a success/failure code. The results of reading a sector - that is, the data in that sector - is transferred into main memory by the DMA controller chip covered earlier.

XT / AT Interchange Problems

As mentioned above, PC/XT 360 KByte drives format disks with 40 tracks, spaced at 48 tracks per inch. The AT, on the other hand, formats a disk with 80 tracks and a spacing of 96 tpi.

It therefore follows that the AT drive read/write head has a much narrower head gap (to fit more tracks in the same space). The first corollary of this is that the media used with this drive must have a higher coercivity - typically around 640 Oersteds - and that ordinary ("double density") media will not work reliably as a result. Attempts to format conventional diskettes in such a drive will result in lots of bad sectors on all but the outermost tracks. Diskettes for use with AT-class machines should be a "High Density" or "High Capacity" type.

Hard Disk Controllers

While the basic principles of operation of hard disks are similar to those of floppy disks, the detail varies considerably.

A hard disk is a sealed unit, and as a consequence, the media are generally not removeable. Exceptions, of course are mainframe disk packs, and Winchester disks, in which the heads are removed, along with the media, in a sealed unit. A number of manufacturers have recently started to offer similar sealed units for PCs, most notably the Plus Passport and Tandon's removeable cartridges..

While a floppy disk has only two sides, a hard disk will often have more. The central spindle will carry two, three, four or more platters, and since each has two sides, this will give the disk up to eight or more sides. Quite often, a hard disk will have seven sides, and this seemingly improbable configuration comes about because one of the sides is used to provide servo head-positioning information.

Most hard disks spin at 3600 rpm, twelve times faster than a floppy, which in part accounts for the faster access time and higher data transfer rates achievable with hard disks. The heads are positioned much more accurately, since there are more tracks per inch, and head motion is usually controlled either by a stepper motor (in older, slower drives) or by a voice-coil mechanism. This gets its name because it works in essentially the same way as the voice-coil which throws the cone of a loudspeaker forward and backwards.

The heads of a hard disk drive do not actually touch the surface of the platters, except when the drive is at rest. Instead, when the drive spins up to speed, friction causes a boundary layer of air next to each platter to start to move with it, and the heads are aerodynamically shaped so that they fly through this layer of air, just above the surface of the platter.

However, should shock or vibration cause the head to come into contact with the platter, the result is a head crash, in which the head gouges into the media. The resultant damage is only repairable by replacement of the platter, which is often uneconomic.

__Hard disks are not required to be able to interchange media in the same way as floppy drives, so there is no standardization of formats. When you first install a had disk, or when performing periodic preventive maintenance, you will have to perform a low-level format on the drive, and this will require you to know the drive's format parameters. These include the number of tracks, number of sides or platters, number of sectors per track, and for some drives, the cylinders at which to reduce write current and introduce write precompensation.

The article on hard disk formatting in the May 1988 issue of PCSA is a good starting point for obtaining much of this information. Whenever you buy a machine or drive, you should also purchase the appropriate technical reference manuals or data sheets, or at least ask the supplier for the drive parameters, as it is much easier to obtain such information then than later.

Many drives conform to the ST-506 interface, which gets its name from some of Shugart's early drives. A useful point to remember is that ST-506-formatted drives usually have 17 sectors per track.

Since the number of sectors per track is constant across the drive surface, those tracks towards the center of the disk pack the data into a lot less space. This is why, at a certain cylinder, the head write current is reduced in order to pack the data in. In addition, the frequency response of the drive circuitry is modified, in essence to sharpen its response to the tightly-packed data. Fortunately it all works whether you understand it or not!

When low-level formatting a drive, there are two important points to bear in mind. First, you should format the drive in its intended operating position. In other words, if you are going to stand the machine vertically, then the LLF should be done with the machine in that position. Generally speaking, there is no difficulty with operating a drive in the conventional desktop position or mounted on its side (although some drives should not be operated mounted vertically on their faceplate or with the faceplate on top). However, gravity will inevitably have some influence, particularly on the read-write head, which must be extremely accurately positioned. A reformat will therefore be required after turning a machine on its side. Generally, those drives which have servo-positioning information on a reserved platter cannot be operated in other than the flat position, since that positioning information cannot be rewritten.

The other point is that you should allow the machine to reach its normal operating temperature before formatting. Metal parts expand and contract, and electronics changes slightly in performance, due to temperature changes. In some extreme cases, the temperature difference may be so great that a drive will operate when warm but not when cold or vice versa! This would usually be considered adequate grounds for warranty exchange or repair, unless your environment is outside the stated range for the drive.

Hard disks are usually more rugged than people believe, being able (typically) to withstand 30G shocks when powered off. However, as a matter of course you should treat drives with care. If your drive does not automatically park its heads upon powering down, then run a head-parking program before switching the machine off. This either retracts the heads off the media, moves the heads in towards the center spindle and off the data area, or positions the heads over the last track where a crash is likely to cause the least damage.

Hard disk controller electronics are a little more complex than for floppy disk drives, because of the higher performance, the need for write precompensation and other factors. For example, because of the greater data density on these drives, the controllers incorporate Error Checking and Correction (ECC) circuitry, so that occasional media defects can be coped with. Generally, hard disk controllers use two cables to attach to the drives. The first is a control signal cable, which may have two connectors crimped onto it for two drives. The question of drive select decoding is a little more complex than for floppy disk drives, and the cable may, or may not, have a twist in it. The controller will usually have two connectors for separate data cables. Most controllers are restricted to handling two drives, although it is possible to install two controller cards in a machine for three or four hard disks.

Some drives do not use the ST-506 interface, but instead use SCSI (often pronounced 'scuzzy') and ESDI interfaces. SCSI (Small Computer System Interface) has been around for some years, and has mostly been popularised by its use on the Macintosh. It is a bus which allows a number of peripherals (hard disks, MIDI controllers, scanners and the like) to be daisy-chained and provides reasonably high rates of data transfer. ESDI (Enhanced Small Device Interface) is found on larger, high-performance drives typically found in 80386-based systems such as file servers. The older SMD (Storage Module Drive) interface is rarely encountered on PCs these days.

Another term you will hear frequently today is RLL. Run Length Limited encoding is a technique which takes over where MFM left off in packing more data into a drive. There are two major types in common use: RLL (2,7) achieves typically a 50% improvement in drive capacity, while RLL (2,9) can pack up to 90% more data into a drive. However, you don't get something for nothing: because RLL packs more data into the drive, the frequency of the signals coming off the media also increases, and the circuitry of some drives simply can't cope. Other drives have a frequency response tailored to not support RLL encoding, usually because the manufacturer wants to sell you the same drive with slightly modified electronics for RLL use, at a higher price, of course.

Some Notes on IDE Drives

The majority of low-cost 286- and 386- based clones and compatibles shipped over the last year or so have used a new low-cost, high-performance type of drive. Older machines usually have drives which use the ST-506/ST-412 drive interface, and controllers which can handle a total of three drives, both floppy and fixed.

The new drive/controller combination is referred to as Integrated Drive Electronics (IDE) or sometimes as an AT-type controller. The best-known manufacturer of IDE drives is Conner Peripherals, a company which is partly owned by Compaq, and in fact Compaq was one of the first users of these drives in its portables. However, IDE has been adopted by other manufacturers, such as Imprimis (CDC), Fuji, Miniscribe, Peripheral Technology and Western Digital.

As the name suggests, an IDE drive has the controller circuitry on the drive itself, rather than a PC-expansion-bus card. As a result, the IDE drive has a logic-level interface, rather like a SCSI drive. ST-506 and ESDI drives require commands to drive the heads to the appropriate track and read the appropriate sector from the specified head, and this in turn requires the machine's BIOS to 'understand' the drive's format.

IDE has much in common with SCSI, but is much less expensive, particularly since many machines now have an IDE controller on the system board. It also provides performance usually equal to, or better than, ESDI drives.

An IDE drive is viewed, by its 'controller' as a randomly accessible stream of sectors, numbered from one upwards. The 'controller' simply sends commands to the drive to read/write sector n, and the drive works out the cylinder, head and sector numbers internally.

The beauty of this scheme is that the drive must internally translate logical sector numbers to physical sector numbers, and this makes it easy to make the drive appear to have any of a number of possible formats. An example will make this clear.

A Conner Peripherals CP3204 drive is a 209 MB 3 1/2" drive which internally is formatted as 8 sides, 1348 cylinders, 38 sectors per track. In order to install this drive into a machine, you will have to find an entry in the machine's BIOS which corresponds to this machine. While many older machines do not have it, newer machines will; for example, recent Phoenix BIOSes have an entry for the CP3204 as type 41.

However, an attempt to install and format the drive using this entry will run into some difficulty. While low-level formatting and diagnostics programs will work OK, you may well run into difficulty when attempting to partition the drive using the DOS FDISK command. Most versions of DOS expect the BIOS to have only a ten-bit field for the number of cylinders on the drive, and this in turn imposes a limit of 1024 cylinders on the drive.

Generally, FDISK will pick up only the lower ten bits of the cylinder count, thereby seeing only (in this case) 1348 - 1024 = 324 cylinders, and format the first 47 MB of the drive. It is particularly annoying when using the automatic installation routines of DOS and especially OS/2, as it can take some time, and quite a few diskette swaps, before you find that the operating system can only see less than one quarter of your expensive drive.

In this situation, many BIOSes provide a way out, in the form of user-definable drive table entries. In the case of the Phoenix BIOS, for example, entries 46 and 47 can be entered by the user for any drive, and subsequently stored in non-volatile memory.

For the CP3204, for example, the easiest fix would be to tell the BIOS that the drive has half as many cylinders, but twice as many heads - in other words, that its format is 674 cylinders, 16 heads, 38 sectors per track. Remember, the IDE drive does not care; the controller simply turns the side, track and sector number into some unique logical sector number, and the drive reads or writes it.

Once the BIOS has had the revised entry set up, the drive should now partition and format normally. Users experiencing difficulty installing OS/2 should format the drive as a DOS 4.01 large logical drive first; OS/2 will then see the drive correctly and will reformat it to HPFS if desired.

Older machines often do not have an entry for the CP3204 or other large IDE drives, and many will not support user-defined drives. For example, a CP3204 would be an ideal upgrade for a Compaq Portable 386, but the machine's BIOS drive table will not support it, although Compaq are rumoured to be considering a BIOS upgrade. In this case, you will encounter difficulty in supporting large drives, although SCSI drives which can boot and then load a device driver to access the entire drive can provide a good solution - at a price; good SCSI controllers are not cheap.

When running IDE drives of any size under DOS, you will also find that utilities which set the interleave factor, such as SpinRite and Disk Optimizer, will not work. This is not a problem, however; the optimum interleave factor will vary with different drive/controller combinations - but the IDE drive already has its own on-board controller, and the drive is formatted by the manufacturer with the optimum interleave factor.

Conner Peripherals Drive Formats

Drive Cylinders Heads Access Time Size
CP344 788 4 28ms 40 MB
CP3044 788 4 25ms 40 MB
CP3184 832 6 25ms 80 MB
CP3104 766 8 24ms 104 MB
CP3204 1348 8 16ms 209 MB

Bibliography

AP-59, "Using the 8259A Programmable Interrupt Controller", Intel Corporation, 1979

Biggerstaff, Ted. J., "Systems Software Tools", Prentice-Hall, 1986. A good introduction to communications and other low-level hardware-related programming on the PC.

"IBM Personal Computer Hardware Reference Library - Technical Reference", IBM, 1981 (Revised 1983). This, and its companions for the XT, AT and the PS/2 range, are indispensable for low-level detail on these machines.

"IBM Personal System/2 Model 50 and 60 Technical Reference", IBM, 1987. Less generally useful than the earlier manuals from IBM, but still indispensable, particularly if you want to understand the Micro Channel Architecture and the VGA. Model 50 and 60 Technical Reference", IBM, 1987. Less generally useful than the earlier manuals from IBM, but still indispensable, particularly if you want to understand the Micro Channel Architecture and the VGA.

"Compaq Portable 386 Personal Computer Technical Reference Guide", Compaq Corp., 1987. This, and its equivalents for other Compaq machines, contains indispensable information for programmers.